Non-volatile memories (NVMs), such as NAND flash chips, suffer from a phenomenon called “read disturb”. Read disturb refers to a condition where reading one cell in a NAND string (i.e., one bit of one page in a block) disturbs (causes errors in) all the other bits in the same string. The other bits are affected because to read one bit in a NAND string, a bypass current is applied to the gate of all the other bits in the NAND string. The bypass current acts as a weak form of programming, changing the charge distribution of the other bits and causing errors to accumulate in the other bits.
Reading a single page repeatedly will not cause read disturb errors on that page. However, the other pages in the same block (i.e., sharing the same NAND strings) as the page being read get disturbed and can accumulate additional errors. Read disturb acts as one source of errors in NAND flash. Other sources of errors can include but are not limited to (i) program disturb, (ii) retention, and (iii) erase and program noise. Program disturb errors are caused by inter-cell interference due to initial programming of adjacent cells. Retention errors are caused by loss of charge over time. Erase and program noise errors is due to imperfect erasing and/or programming.
A conventional method for preventing data loss due to the above errors is for a vendor to specify an error correction level that accounts for the effects, within certain limits. In one example, devices are rated with a vendor-specified “read disturb limit” such that read disturb does not cause excess errors (i.e., beyond the rated error correction level) as long as a read count (i.e., a count of the number of reads since the last erase/program) within a block is kept below the vendor-specified “read disturb limit.” Similarly, a retention rating is provided such that retention loss will not cause excess errors over a specified period of time as long as the NAND flash chips are kept within a specified temperature range.
The read disturb limit is a number of reads of a given block after which the data in that block will be so disturbed (i.e., will have accumulated so many additional errors due to the reading operations) that the block should be re-written (i.e., the data should be copied to a new location), and the given block erased. The erased block can then be used as “new” for other data. Copying data to a new location is sometimes called garbage collection or recycling.
Recycling also is performed independent of read disturbs to reclaim free space that is generated when data is overwritten. For example, a Host, coupled to a Solid-State Disk (SSD) comprising NAND flash, writes first data to address X, and later writes second data to address X, rendering the first data unused. Because of the nature of NAND flash, the second data is stored in a different location in the SSD than the location of the first data. The location of the first data becomes unused and is re-claimed by recycling. The second data is sometimes referred to as “active” or “in-use” data, and the no-longer-used first data is sometimes referred to as “a hole.” The NAND flash becomes a Swiss cheese of active data and holes over time. The free space represented by the holes needs to be reclaimed by recycling, for example, through periodic “read scrubs.”
Each “read” in the read disturb limit is (defined as) a sequential read of all of the pages in a block. For example, a read disturb limit of 10K would mean that a given block, once programmed, can be sequentially read ten thousand times before the cells were so disturbed as to need corrective action. This would mean that every page in the block could be read 10K times (i.e., sequentially read the block 10K times). Looking at the disturb effect, each page gets (# pages−1)*10K disturbs (because each page is disturbed by all reads other than its own. Counting on a block basis, the safe limit is (# pages−1)*10K in this case.
Read disturb limits generally decrease with lifetime. As the NVM wears (e.g., as program/erase cycles increase for NAND flash), the read disturb limit gets lower. Typically, a conventional MLC (multi-level cell) NAND chip might have a read disturb limit of 10K near the beginning of its life (i.e., no or few program/erase cycles) and a read disturb limit of 1K at the end of its life (i.e., at/near the rated number of program/erase cycles).
It would be desirable to implement a read disturb effect determination.